1. Field of the Invention
The present invention relates to a semiconductor device employing dynamically reconfigurable circuit technology.
2. Description of the Related Art
In recent years, the functionality and complexity of portable electronic devices, and other devices that require low cost and power consumption, has increased. In order to maintain high performance and low power consumption, development and manufacture of dedicated hardware are indispensable techniques. However, as device complexity increases and more functionality is required of devices, the costs of development and manufacture of dedicated device hardware increases. Much attention is now being paid to semiconductor devices employing dynamically reconfigurable circuit technology, as such devices are capable of reducing such manufacture and development costs.
Semiconductor devices using dynamically reconfigurable circuit technology are equipped with a reconfigurable circuit such as an FPGA and a storage device for storing several pieces of circuit information. The circuit information is used for constructing various circuits (hereinafter referred to as “execution circuits”) that are part of the reconfigurable circuit. Execution circuits can be constructed during operation by reading circuit information according to rules that are determined in advance by software or the like. Reconfigurable devices are different from conventional semiconductor devices using an FPGA in that they can change execution circuits during operation.
Reconfigurable semiconductor devices are expected not only to reduce the development cost of dedicated hardware like FPGAs do, but also to reduce the manufacturing cost of dedicated hardware. The manufacturing cost is expected to be reduced because a variety of functions can be implemented on a small semiconductor device by dynamically constructing execution circuits.
Known examples of semiconductor devices employing dynamically reconfigurable circuit technology are the DRP (dynamically reconfigurable processor) by NEC Electronics Corporation and PipeRench by Carnegie Mellon University.
The DRP has a structure using PEs (processing elements) as basic elements for computation. The PEs are arranged as a two-dimensional array, and a state transition controller is located at the center of the PE arrangement. The PEs are computing devices capable of constructing execution circuits. Several pieces of circuit information are stored in an instruction memory provided in each PE. The circuit information can include the type of computation to be performed by the PE, or information on connections between PEs. Each PE dynamically constructs an execution circuit by reading the circuit information from an instruction memory. The instruction memory is read at a location determined by an instruction pointer that is provided by a state transition controller.
In PipeRench, several PEs are used as basic elements for computation and a “stripe” (the PEs and a bus connecting the PEs) is used to connect the PEs in a pipeline. The PEs are computing devices capable of constructing execution circuits. The PEs are connected via a global bus to a control device which is located outside PipeRench. Circuit information such as the type of computation to be performed by a PE, or information on bus connections for each PE, is transferred from the control device located outside PipeRench to each PE via the global bus. Each PE dynamically constructs an execution circuit according to the circuit information.
To achieve good performance with a dynamically reconfigurable semiconductor device, it is desirable to shorten the time necessary to reconfigure the device. The steps in reconfiguring the device include: determining the circuit information to be used for construction of an execution circuit; constructing an execution circuit according to the circuit information; and performing a computation on input data that arrives approximately when the execution circuit is constructed.
In PipeRench, the external control device transfers circuit information directly to each PE in order to construct the execution circuits. Thus, there can be a long delay between when the control device determines what circuit information to use and the construction of the execution circuits in the PEs. The result is that it may take a long time to reconfigure the device.
In the DRP, each PE is configured to store several pieces of circuit information in an instruction memory. When constructing an execution circuit, each PE reads out circuit information from the instruction memory. Thus, the time taken for transferring circuit information is shortened and it may take less time to reconfigure the device.
In the DRP, the state transition controller first detects an event that input data has reached a PE. Then the state transition controller determines the circuit information necessary to construct an execution circuit in the PE, and gives the PE an instruction pointer. The PE then reads the circuit information from the instruction memory at the location identified by the instruction pointer.
Thus, the circuit information required to construct an execution circuit is not determined until the arrival of the input data at the PE. This can lengthen the amount of time that is required to reconfigure the device.
Even if dynamically reconfigurable circuits were connected to each other in the same manner as in PipeRench and the DRP approach were used to reconfigure the device, the possibility of delay would still exist.